Flash memories are non-volatile read-write memory devices. Flash memories can be used in various electronic devices, such as mobile-phones, computers, digital cameras, MP3 players and the like. A flash memory can include multiple flash cells. A flash cell can include a control-gate transistor and a floating-gate transistor. Typically, each flash cell retains a single bit of information.
There are various types of flash cell technology. In one such technology, flash cells are arranged in matrix structures. A matrix is an arrangement of flash cells including multiple bit lines and multiple word lines. Different types of flash memory can be obtained based on the particular matrix configuration. For example, NOR flash memory or NAND flash memory can be obtained depending on the manner in which flash cells are connected to bit lines within the matrix. Exemplary matrix configurations of a NOR flash memory and a NAND flash memory are depicted in FIGS. 1(a) and 1(b), respectively.
FIG. 1(a) shows an exemplary NOR flash memory matrix arrangement. For simplicity, only eight word lines and two bit lines are depicted in FIG. 1(a). In this matrix, flash memory gate terminals are connected to word lines (WL<0> through WL<7>), drain terminals are connected to bit lines (BL<0> and BL<1>), and source terminals are, connected to a common source line (SL).
FIG. 1(b) shows an exemplary NAND flash memory matrix arrangement. Again, for simplicity, only eight word lines and two bit lines are depicted in FIG. 1(b). Flash cells are grouped into so-called strings or blocks of cells. An individual string/block (hereinafter referred to as “string”) is a group of several flash cells connected in series. In this example, a string is indicated by the dotted line and includes four flash cells. Drain terminals of the string are connected to bit lines (BL<0> and BL<1>) through a drain selector transistor (DST), and source terminals of the string are connected to a common source line (SL) through a source selector transistor (SST). Gate terminals of the flash cells are connected to word lines (WL<0> through WL<7>), and gate terminals of the selector transistors are connected to selector lines (DSL<0>, DSL<1>, SSL<0>, and SSL<1>).
In both flash architectures, as shown in FIGS. 1(a) and 1(b) for example, a p-well bulk region, which is a p-type semiconductor well, can be common to (i.e., shared by) multiple flash cells and/or multiple strings. If the p-well bulk region includes all of the flash cells in the memory, then the memory is considered to be a single-plane flash. If some flash cells are drawn in different p-well bulk regions, then the memory is usually considered to be a multi-plane flash.
During use of a flash memory, the various flash cells will typically need to be erased. Erasure of multiple flash cells in both NAND and NOR flash memory can be accomplished by exploiting the Fowler-Nordheim (FN) tunnel effect. The FN tunnel effect permits the extraction of charge stored in flash cells (thereby erasing them) by applying a high voltage difference between the p-well bulk region and the gate of the cell. This causes the flash cells to assume a high voltage, equivalent to a binary “1,” which can correspond to an erase state of the cells.
In NAND matrix and in some NOR matrix flash memories this can be achieved by raising the p-well bulk region to a high voltage value (such as 15V or more, for example) and keeping grounded the word lines or group of word lines of the cells to be erased. All other word lines (i.e., those of cells not to be erased) are left floating. Accordingly, when the p-well bulk region is raised to a high value, only those flash cells located along word lines kept to ground or to a low potential voltage are erased. This is because a high voltage difference is developed between their p-well bulk region(s) and gate terminals, thus permitting the FN tunnel effect to take place. In contrast, because the other word lines are left floating, they are coupled to the high erase voltage. Accordingly, a zero voltage difference is developed between the p-well bulk region(s) and gate terminals of the flash cells along these word lines, thus inhibiting the FN tunnel effect.
During an erase pulse, that is, during the erase phase in which the p-well bulk region is raised to a high voltage, the common source line can be shorted to the p-well bulk region. An electronic component such as a switch circuit can be used to short the p-well bulk region and the common source line. However, the bit lines can be left floating to avoid cell damage and p-n junction breakdown.
FIG. 2 shows an exemplary circuit that can be used in NAND flash memory to interface bit lines with a page buffer read block and other circuits. For simplicity, only two bit lines are depicted in FIG. 2. A typical flash memory will have many more bit lines. As can be seen, there are two paths through the interface circuit. The first path, through transistors M1<0> and M1<1>, connects the bit lines to SENSE_NODE. SENSE_NODE can be a low-voltage sensing node for the page buffer. The second path, through transistors M2<0> and M2<1>, connects the bit lines to SERVICE_NODE. SERVICE_NODE can be used for several different purposes, such as pre-charging bit lines during read or program, or shielding a read bit line from adjacent read bit lines during read or verify. SERVICE_NODE can be connected to an analog switch to allow biasing at the desired voltage level.
The transistors shown in FIG. 2 can be high-voltage transistors, meaning that they can sustain a high voltage difference between their terminals. Gate connections are not depicted in FIG. 2 for simplicity. During an erase pulse, all the bit lines can be left floating by driving the gate terminals of the interface transistors M1<0>, M1<1>, M2<0> and M2<1> to ground or to a low voltage level. Since the bit lines are left floating during an erase pulse, all the bit lines rise to the same voltage that is applied to the p-well region.
This rising of the bit lines can be caused by two effects. First, the p-well bulk region, the non-erasing word lines, and the common source-line strap can be capacitively coupled to bit lines. (The common source-line strap is a grid of metal lines connecting source line taps. These metal lines are typically drawn with a higher metal level than the bit lines.) Second, the p-n junctions corresponding to the contacts of the bit lines can be forward biased, thus permitting the flow of current. These two effects are described in more detail below with reference to FIG. 3.
FIG. 3 shows a section of a NAND flash memory matrix along the bit-line direction. The p-well bulk region (P-well matrix bulk) is separated from the p-well substrate (p-substrate) of the chip by means of deep-n-well diffusion. The deep n-well is usually shorted to the p-well bulk region. The word lines can be made of polysilicon, the bit lines can be made of a first metal (MET1), and the common source line grid can be made of a second metal (MET2).
As stated above, FIG. 3 illustrates the two effects that ensure the rise of the floating bit lines during the erase pulse. The capacitive coupling is represented by the parasitic capacitance elements and the forward biasing of the contact junction is represented by the parasitic p-n junction diodes. Note, however, that the parasitic capacitive coupling between bit lines and the grounded word lines to be erased does not contribute to the rising of the bit lines.
In prior methods, when the erase pulse is finished, the p-well bulk region and common source line are discharged together by means of a discharger circuit. The bit lines, on the other hand, are discharged only by the capacitive coupling effect. Since the contact junctions of the bit lines are reverse biased during discharge, they only contribute to the bit-line discharge with their reverse bias parasitic capacitance.
The present inventors have recognized that at the end of the discharge process in the erase operation, while the value of the bit lines is generally low, the precise value is unknown and can actually be considerably higher than ground. In addition, if capacitive coupling between the p-well bulk region and the bit lines is not efficient during discharge, there is a risk of triggering unwanted junction breakdown due to a possible voltage difference that can build up between the p-well bulk region and the bit lines.
The inventors have also recognized that these drawbacks can be exacerbated when multiple word lines or multiple blocks are erased simultaneously. In these circumstances, the capacitive coupling might be weaker because many word lines are biased to ground and thus may shield the capacitive coupling effect from the p-well bulk region to the bit lines. While this might not impact the rising of the bit lines since that effect can occur by the forward biasing of the p-n contact junction, it can have a negative impact during the discharge phase when bit line discharge is done solely by capacitive coupling. All of these problems can lead to damage or premature aging of the flash cells and/or interface transistors. This can have a negative influence on the reliability, endurance, and retention capabilities of the flash memory.